
Jacqueline E. Rice, Professor
Dept. of Math and Computer Science
University of Lethbridge
4401 University Drive
Lethbridge, Alberta, Canada T1K 3M4
tel: 403.329.2783 fax: 403.317.2882






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Student coauthors are indicated in bold.
You may also be interested in my google scholar page.
2017
Md. A. Nashiry,, M. H. A. Khan, and J. E. Rice,
"Controlled and Uncontrolled SWAP Gates in Reversible Logic
Synthesis", to appear in Proceedings of the
International
Conference on Reversible Computation, Kolkata, India, July 67 2017.
2016
Musharrat Khan and Jacqueline E. Rice, “Ternary MaxMin Algebra for Representation of Reversible Logic Functions,” to appear in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) Montreal, Canada, 2016,
pp. 16701673.
Musharrat Khan and Jacqueline E. Rice, “Synthesis of Reversible Logic Functions using Ternary MaxMin Algebra,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) Montreal, Canada, 2016, pp. 16741677.
Mozammel H A Khan and Jacqueline E. Rice, “Improved Synthesis of Reversible Sequential Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (special session on reversible logic) Montreal, Canada, 2016,
pp. 23022305.
Md. Z. Rahman and J. E. Rice, "Template Matching with Ranking for Toffoli Circuits,"
International Journal of Computer and Information Technology (IJCIT) ISSN: 22790764, vol. 5, no. 1, pp. 18–24, Jan. 2016. [pdf]
2015
M. A. Nashiry, G. G. Bhaskar and J. E. Rice, “Online Testing for Three Fault Models in Reversible Circuits,” in Proceedings of the 2015 IEEE International Symposium on MultipleValued Logic (ISMVL), 18–20 May, Waterloo, Canada, 2015, pp. 8–13, doi: 10.1109/ISMVL.2015.36. [pdf]
F. Naz and J. E. Rice, “Sociolinguistics and Programming,” in Proccedings of the 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 24–26 Aug., Victoria, Canada, 2015, pp. 74–79, doi: 10.1109/PACRIM.2015.7334812. [pdf]
J. Law and J. E. Rice, “Line Reduction in Reversible Circuits using KFDDs,” in Proceedings of the 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 24–26 Aug., Victoria, Canada, 2015, pp. 113–118, doi: 10.1109/PACRIM.2015.7334819. [pdf]
2014
"Reversible Logic: a stepping stone to quantum computing?", J. E. Rice,
Encyclopedia of Information Science and Technology, 3rd Edition.
IGI Global, 2015. 72717279. available for purchase from
IGI Global
"Concept Vocabularies in Programmer Sociolects",
JE Rice, B Ellert, I Genee, F Taiani, and P Rayson,
in the Proceedings of the
25th Annual Workshop of the Psychology of Programming Working Group (PPIG),
Brighton, UK,
June 2014 [pdf]
"Linking Linguistics and Programming: How to start?",
JE Rice, I Genee, and F Naz,
in the Proceedings of the
25th Annual Workshop of the Psychology of Programming Working Group (PPIG)
Brighton, UK,
June 2014 [pdf]
"Templates for Positive and Negative Control Toffoli Networks",
MZ Rahman, and JE Rice,
in the Proceedings of the 6th Conference on Reversible Computation
(RC 2014), Springer Lecture Notes in Computer Science, Vol. 8507,
Yamashita, Shigeru, Minato, Shinichi (Eds.)
pp. 125136,
July 2014, Kyoto, Japan. [pdf]
2013
"An Overview of Fault Models and Testing Approaches
for Reversible Logic"}, J. E. Rice, in the Proceedings of the
2013 Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM), Aug. 2013,
Victoria, BC, Canada, pp. 125130
[pdf]
"Online Testable Approaches in Reversible Logic",
J. E. Rice and N. M. Nayeem,
Journal of Electronic Testing, Theory and Application
(JETTA)
[pdf]
vol. 29, issue 6, pp. 763768, Dec. 2013. available
online from Springer at
http://dx.doi.org/10.1007/s1083601353993
"A Modular Approach to Designing an Online Testable Ternary Reversible Circuit",
J. E. Rice and R. Rahman, International
Journal of Computer Science (IJICS),
vol. 2, no. 5, pp. 6676,
July 2013
[pdf]
2012
"What is Middleware Made Of? Exploring abstractions,
concepts, and class names in modern middleware",
F. Taiani, J. E. Rice and P. Rayson,
accepted for presentation at ARM2012
[pdf of preliminary version]
"Design of an Online Testable Ternary Circuit from the Truth Table",
N. M. Nayeem and J. E. Rice, accepted for presentation at the
4th Workshop on Reversible Computation (RC2012)
Copenhagen, Denmark
July 23, 2012
[pdf]
"Feasibility Evaluation of a Secured Architecture for 2party Mobile Payments (SA2pMP)",
Y. Zhu, J. E. Rice, B. Dobing, G. Shan, and M. Dong,
in the proceedings of the
2012 IEEE/ACIS 11th International Conference on
Computer and Information Science (ICIS),
pp. 277  282
May 3031 2012, Shanghai, China.
doi: 10.1109/ICIS.2012.49
"A New Approach to Online Testing of TGFSOPbased Ternary Toffoli Circuits",
N. M. Nayeem and J. E. Rice,
in the proceedings of the
International Symposium on MultipleValued Logic (ISMVL),
1416 May 2012,
Victoria, BC, Canada,
pages 315  321.
doi: 10.1109/ISMVL.2012.57
[pdf]
2011
"A Sharedcube Approach to ESOPbased Synthesis of Reversible Logic"
N. M. Nayeem and J. E. Rice,
in Facta Universitatis Series: Electronics and Energetics
(ISSN 03533670)
volume 24 issue 3, pages 385403; 2011
[pdf]
"Online Fault Detection in Reversible Logic",
N. M. Nayeem and J. E. Rice,
in the Proceedings of
the 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT),
35 October, 2011, Vancouver, BC, Canada, pages 426434,
doi: 10.1109/DFT.2011.55 .
[pdf]
"A Simple Approach for Designing Online Testable Reversible Circuits",
N.M. Nayeem and J. E. Rice,
in the Proceedings of the 2011 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August, 2011, Victoria, B.C., Canada, pages 274279.
[pdf] (BEST PAPER)
"Ordering Techniques for ESOPBased Toffoli Cascade Generation",
N. M. Nayeem and J. E. Rice,
in the Proceedings of the 2011 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August, 2011, Victoria, B.C., Canada, pages 274279.
[pdf]
"On Designing a Ternary Reversible Circuit for Online Testability",
Md. R. Rahman and J. E. Rice,
in the Proceedings of the 2011 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August, 2011, Victoria, B.C., Canada, pages 119124.
[preliminary pdf]
"Improving ESOPbased Synthesis of Reversible Logic",
N. M. Nayeem and J. E. Rice,
in Proceedings of the 2011 RM Workshop,
Tuusula, Finland, May 2526, pp. 5762.
[pdf]
"Online Testable Ternary Reversible Circuit",
M. R. Rahman and J. E. Rice,
in Proceedings of the 2011 RM Workshop,
Tuusula, Finland, May 2526, pp. 7179.
[pdf]
"New Considerations for Spectral Classification of Boolean Switching Functions", J. E. Rice, J. C. Muzio and N. Anderson,
VLSI Design, vol. 2011, Article ID 356137, 9 pages, 2011.
doi:10.1155/2011/356137
[online article]
2010
"Systolic Array Technique for Determining Common Approximate
Substrings", J. E. Rice and K. B. Kent,
Journal of Computer Science and Engineering,
May 2010, Volume 1, Number 1, pp. 19 [pdf]
"Using Autocorrelation Coefficientsbased Cost Functions
in ESOPbased Toffoli Gate Cascade Generation", J. E. Rice and
V. Suen, in the proceedings of the 23rd IEEE Canadian Conference
on Electrical and Computer Engineering (CCECE),
Calgary, Canada, May 2010, pages 16
[pdf]
2009
"Properties of Autocorrelation Coefficients for SingleOutput
Switching Functions", J.E. Rice, J.C. Muzio, N.A. Anderson and
R. Jansen,
International Journal of Computer Theory and Engineering (IJCTE), December 2009,
Volume 1, Number 5, pp. 546555
[pdf]
"A Lightweight Architecture for Secure TwoParty Mobile Payment",
Y. Zhu
and J. E. Rice, in the Proceedings of the International Conference
on Computational Science
and Engineering (CSE)
August 29  31, Vancouver, B.C., Canada,
Volume 2 pages 326  333 [pdf]
"A Proposed Architecture for Secure TwoParty Mobile Payment", J. E. Rice and
Y. Zhu, in the Proceedings of the
2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing August 2326, 2009, University of Victoria, Victoria, B.C., Canada,
pages 88  93
[pdf]
"The Autocorrelation Transform and its Application to the Classification of Boolean Functions", J. E. Rice, in the Proceedings of the
2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing August 2326, 2009, University of Victoria, Victoria, B.C., Canada,
pages 94  99
[pdf]
"Toffoli Gate Cascade Generation Using ESOP Minimization and QMDDBased
Swapping", J.E. Rice, K. Fazel,,
M. Thornton and K. B. Kent, in the Proceedings of
the ReedMuller Workshop,
May 2324 2009, Okinawa, Japan, pp. 6372.
[pdf]
"Case Studies in Determining the Optimal FPGA Design for Computing Highly Parallelizable Problems", J.E. Rice and K.B.Kent,
IET Computers \& Digital Techniques, May 2009
Volume 3, Issue 3, p. 247258.
[pdf]
2008
"An Introduction to Reversible Latches", J. E. Rice,
The Computer Journal 2008 51(6):700709; doi:10.1093/comjnl/bxm116
[online access]. [bibtex pdf]
2007
"Investigating the Implementation of a 2DRtree
on a FPGA", J. E. Rice, J. Schultz and W. Osborn,
in the Proceedings of the
5th Annual IEEE International Northeast Workshop on
Circuits and Systems (NEWCAS), August 58 2007, Montreal,
Quebec, Canada, pp. 646649
[bibtex pdf].
"ESOPbased Toffoli Gate Cascade Generation", J. E. Rice,
M. Thornton and
K. Fazel, in the Proceedings of
the 2007 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August 2224, 2007,
Victoria, B.C., Canada, pp. 206209
[pdf].
2006
"Implementation of a Spatial Data Structure on a FPGA",
J. E. Rice, W. Osborn and J. Schultz, in the
Proceedings of the Second International Joint Conferences on
Computer, Information, and Systems Sciences and Engineering
(CISSE),
December 414 2006, CDROM paper no. 549 (econference), published
by Springer, [pdf].
"An Analysis of Several Proposals for Reversible Latches", J. E. Rice,
in the Proceedings of the Second International
Joint Conferences on
Computer, Information, and Systems Sciences and Engineering
(CISSE), December 414 2006, CDROM paper no. 548 (econference), published
by Springer, [pdf].
"Balancing Motherhood and
a Career in the Sciences",
J. E. Rice, invited paper,
in the 2006 Graduate Students' Association Conference Proceedings
[GSA Proceedings].
(unrefereed)
"Gender and Programming: a sociolinguistic perspective"
(with K. Hansen), in the Proceedings of
the First Annual Gender Symposium, March 4 2006,
University of Lethbridge [symposium proceedings].
(unrefereed)
"A New Look at Reversible Memory Elements",
Authors: J. E. Rice, in the Proceedings of the International Symposium
on Circuits and Systems (ISCAS) 2006, CDRom paper 1628.pdf,
pp. 12431246
[pdf].
"A Systolic Array Techniques for Determining Common Approximate
Substrings",
Authors: J. E. Rice and K. B. Kent, in the Proceedings of
the International
Symposium on Circuits and Systems (ISCAS) 2006,
CDRom paper 1480.pdf
[pdf].
2005
"Reversible Logic Synthesis Example using a Transformation Based
Algorithm" (with B. Gergel), presented at the
ULSI Workshop 2005 [pdf].
(unrefereed)
"Determining a Method for Fast Autocorrelation Classification",
in the Proceedings of the IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing
(PACRIM) 2005, Aug. 2426, Victoria, BC, Canada, CDROM paper number 338,
pages 661664
[pdf].
"Making a Choice Between FDDs and BDDs",
in the Proceedings of
the International Workshop on Logic Synthesis (IWLS), Lake Arrowhead,
California, June 2005, pages 4650
[pdf].
"Symmetrical, Dual and Linear Functions and Their Autocorrelation
Coefficients" (with R. Jansen), in the Proceedings of
the International Workshop on Logic Synthesis (IWLS), Lake Arrowhead,
California, June 2005, pages 3035
[pdf].
"HardwareBased Implementation of the Common Approximate
Substring Algorithm" (with K. B. Kent,
S. Van Schaick, and P. A. Evans),
in the Proceedings of the Euromicro Conference on
Digital System Design (DSD)
August 30  September 3, 2005, Porto, Portugal, pages 314320
[pdf].
"Instancespecific versus Parameterspecific Circuit Generation"
(with K. Kent, T. Ronda and Z. Yong),
in the Proceedings of the Engineering of Reconfigurable Systems and Applications (ERSA) Conference,
part of the International Multiconference on Computer Science and Computer
Engineering, June 2730, 2005, Las Vegas, U.S.A, pages 243246
[pdf].
"Antisymmetries in the Representation of Boolean and
MultiValued Functions" (with J. C. Muzio),
the Proceedings of the
the International Symposium on MultipleValuedLogic (ISMVL),
Calgary, Alberta, May 2005, pages 270275
[pdf].
"Configurable
Hardware Solutions for Computing Autocorrelation Coefficients:
a Case Study" (with K. Kent, T. Ronda and Z. Yong),
in the Proceedings of the International Conference on
Field Programmable Gate Arrays (FPGA) 2005, Monterey California, Feb. 2005
[pdf].
2003
"Properties of Autocorrelation Coefficients" (with J. C. Muzio),
in the Proceedings of the IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
2003, Victoria, Canada, pp. 577580
[pdf].
"Using InstanceSpecific Circuits to Compute Autocorrelation
Coefficients" (with K. Kent),
in the Proceedings of the First Annual Northeast Workshop on
Circuits and Systems (NEWCAS), 2003, Montreal, Canada,
pages 6164
[paper, word doc format].
"On the Use of Autocorrelation Coefficients in the Identification
of ThreeLevel Decompositions",
in the Proceedings of the International Workshop on Logic Synthesis
(IWLS) 2003, Laguna Beach, California, pp. 187191
[ps format]
[pdf format].
"Autocorrelation Coefficients in the Representation and
Classification of Switching Functions", presented at
the first EDAA PhD Forum in conjunction with the
Design, Automation and Test in Europe Conference (DATE),
2003, Munich, Germany.
[abstract, ps format]
[poster, ppt format].
PhD Dissertation: "Autocorrelations Coefficients in the
Representation and Classification of Switching Functions",
University of Victoria, 2003
[zipped ps
format].
2002
"Use of the Autocorrelation Function in the Classification of
Switching Functions" (with J. C. Muzio),
in the Proceedings of the Euromicro Symposium
on Digital System Design: Architectures, Methods and Tools (DSD),
2002, Dortmund, Germany, pp 244251
[ps format].
"Antisymmetries in the Realization of Boolean Functions" (with J. C. Muzio),
in the Proceedings of the International Symposium on Circuits and
Systems (ISCAS 2002),
May 2629, Scottsdale, Arizona [ps format] [pdf format].
2000
"Methods for Calculating Autocorrelation Coefficients" (with J. C.
Muzio and M. Serra), in the proceedings of the
4th International Workshop on Boolean Problems Sept. 2122 2000,
Freiberg, Germany, pp 6976
[ps format] [presentation].
1999
"The Use of Autocorrelation Coefficients for Variable Ordering for ROBDDs"
(with J. C. Muzio and M. Serra) in the Proceedings of
the 4th International Workshop on
Applications of the ReedMuller Expansion in Circuit Design 1999,
pages 185196
[ps format].

TRCSJR12005: Projects Background in Reversible Logic
TRCSJR22005:The
State of Reversible Sequential Logic Synthesis
TRCSJR22007:Considerations for Determining
a Classification Scheme for Reversible Boolean Functions
TRCSJR12012: ESOPbased methods for Toffoli gate cascade generation
TRCSJR22012: Sociolinguistics in Programming: Background Material
Bibliography of Papers related to Reversible Logic
SYNTHESIS AND TESTING
OF REVERSIBLE TOFFOLI CIRCUITS MSc thesis,
N. M. Nayeem, University of Lethbridge, Lethbridge,
Alberta, 2011 (pdf).
ONLINE TESTING
IN TERNARY REVERSIBLE LOGIC, MSc thesis,
Md. Raqibur Rahman, University of Lethbridge, Lethbridge,
Alberta, 2011 (pdf).
A New Architecture For
Secure TwoParty Mobile Payment Transactions,
MSc thesis, Yunpu Zhu, University of Lethbridge, Lethbridge,
AB, 2010 (pdf).
The Classification
of Boolean Functions Using the RademacherWalsh Transform,
MSc thesis, N. Anderson, University of Victoria,
Victoria, BC, 2007 (pdf).
Autocorrelation Coefficients
in the Representation and Classification of Switching
Functions, PhD Dissertation, J.E. Rice,
University of Victoria, Victoria, BC, 2003 (pdf).
Variable Ordering for
ROBDDBased FPGA Logic Synthesis,
MSc thesis, J. E. Rice (nee Crow), University of Victoria,
Victoria, BC, 1995 (ps format).

