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Jacqueline E. Rice, Professor
Dept. of Math and Computer Science
University of Lethbridge
4401 University Drive
Lethbridge, Alberta, Canada T1K 3M4
tel: 403.329.2783 fax: 403.317.2882
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Student co-authors are indicated in bold.
You may also be interested in my google scholar page.
2018
M. H. A. Khan and Jacqueline E. Rice,
"First Steps in Creating Online Testable Reversible Sequential Circuits," VLSI Design, vol. 2018, Article ID 6153274, 13 pages, 2018. doi:10.1155/2018/6153274.
online access
2017
Md. A. Nashiry and J. E. Rice,
"A Reversible Majority Voter Circuit and Applications",
in the Proceedings of the
2017 IEEE Pacific Rim Conference on Communications, Computers and
Signal Processing (PACRIM)},
Aug., Victoria, Canada, 2017. [pdf]
Md. A. Nashiry,, M. H. A. Khan, and J. E. Rice,
"Controlled and Uncontrolled SWAP Gates in Reversible Logic
Synthesis", in Proceedings of the
International
Conference on Reversible Computation, Kolkata, India, July 6--7 2017. [pdf]
2016
Musharrat Khan and Jacqueline E. Rice, “Ternary Max-Min Algebra for Representation of Reversible Logic Functions,” to appear in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) Montreal, Canada, 2016,
pp. 1670--1673.
Musharrat Khan and Jacqueline E. Rice, “Synthesis of Reversible Logic Functions using Ternary Max-Min Algebra,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) Montreal, Canada, 2016, pp. 1674--1677.
Mozammel H A Khan and Jacqueline E. Rice, “Improved Synthesis of Reversible Sequential Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (special session on reversible logic) Montreal, Canada, 2016,
pp. 2302--2305.
Md. Z. Rahman and J. E. Rice, "Template Matching with Ranking for Toffoli Circuits,"
International Journal of Computer and Information Technology (IJCIT) ISSN: 2279-0764, vol. 5, no. 1, pp. 18–24, Jan. 2016. [pdf]
2015
M. A. Nashiry, G. G. Bhaskar and J. E. Rice, “Online Testing for Three Fault Models in Reversible Circuits,” in Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic (ISMVL), 18–20 May, Waterloo, Canada, 2015, pp. 8–13, doi: 10.1109/ISMVL.2015.36. [pdf]
F. Naz and J. E. Rice, “Sociolinguistics and Programming,” in Proccedings of the 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 24–26 Aug., Victoria, Canada, 2015, pp. 74–79, doi: 10.1109/PACRIM.2015.7334812. [pdf]
J. Law and J. E. Rice, “Line Reduction in Reversible Circuits using KFDDs,” in Proceedings of the 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 24–26 Aug., Victoria, Canada, 2015, pp. 113–118, doi: 10.1109/PACRIM.2015.7334819. [pdf]
2014
"Reversible Logic: a stepping stone to quantum computing?", J. E. Rice,
Encyclopedia of Information Science and Technology, 3rd Edition.
IGI Global, 2015. 7271-7279. available for purchase from
IGI Global
"Concept Vocabularies in Programmer Sociolects",
JE Rice, B Ellert, I Genee, F Taiani, and P Rayson,
in the Proceedings of the
25th Annual Workshop of the Psychology of Programming Working Group (PPIG),
Brighton, UK,
June 2014 [pdf]
"Linking Linguistics and Programming: How to start?",
JE Rice, I Genee, and F Naz,
in the Proceedings of the
25th Annual Workshop of the Psychology of Programming Working Group (PPIG)
Brighton, UK,
June 2014 [pdf]
"Templates for Positive and Negative Control Toffoli Networks",
MZ Rahman, and JE Rice,
in the Proceedings of the 6th Conference on Reversible Computation
(RC 2014), Springer Lecture Notes in Computer Science, Vol. 8507,
Yamashita, Shigeru, Minato, Shin-ichi (Eds.)
pp. 125-136,
July 2014, Kyoto, Japan. [pdf]
2013
"An Overview of Fault Models and Testing Approaches
for Reversible Logic"}, J. E. Rice, in the Proceedings of the
2013 Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM), Aug. 2013,
Victoria, BC, Canada, pp. 125--130
[pdf]
"Online Testable Approaches in Reversible Logic",
J. E. Rice and N. M. Nayeem,
Journal of Electronic Testing, Theory and Application
(JETTA)
[pdf]
vol. 29, issue 6, pp. 763-768, Dec. 2013. available
online from Springer at
http://dx.doi.org/10.1007/s10836-013-5399-3
"A Modular Approach to Designing an Online Testable Ternary Reversible Circuit",
J. E. Rice and R. Rahman, International
Journal of Computer Science (IJICS),
vol. 2, no. 5, pp. 66-76,
July 2013
[pdf]
2012
"What is Middleware Made Of? Exploring abstractions,
concepts, and class names in modern middleware",
F. Taiani, J. E. Rice and P. Rayson,
accepted for presentation at ARM2012
[pdf of preliminary version]
"Design of an Online Testable Ternary Circuit from the Truth Table",
N. M. Nayeem and J. E. Rice, accepted for presentation at the
4th Workshop on Reversible Computation (RC2012)
Copenhagen, Denmark
July 2-3, 2012
[pdf]
"Feasibility Evaluation of a Secured Architecture for 2-party Mobile Payments (SA2pMP)",
Y. Zhu, J. E. Rice, B. Dobing, G. Shan, and M. Dong,
in the proceedings of the
2012 IEEE/ACIS 11th International Conference on
Computer and Information Science (ICIS),
pp. 277 - 282
May 30-31 2012, Shanghai, China.
doi: 10.1109/ICIS.2012.49
"A New Approach to Online Testing of TGFSOP-based Ternary Toffoli Circuits",
N. M. Nayeem and J. E. Rice,
in the proceedings of the
International Symposium on Multiple-Valued Logic (ISMVL),
14-16 May 2012,
Victoria, BC, Canada,
pages 315 - 321.
doi: 10.1109/ISMVL.2012.57
[pdf]
2011
"A Shared-cube Approach to ESOP-based Synthesis of Reversible Logic"
N. M. Nayeem and J. E. Rice,
in Facta Universitatis Series: Electronics and Energetics
(ISSN 0353-3670)
volume 24 issue 3, pages 385-403; 2011
[pdf]
"Online Fault Detection in Reversible Logic",
N. M. Nayeem and J. E. Rice,
in the Proceedings of
the 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT),
3-5 October, 2011, Vancouver, BC, Canada, pages 426-434,
doi: 10.1109/DFT.2011.55 .
[pdf]
"A Simple Approach for Designing Online Testable Reversible Circuits",
N.M. Nayeem and J. E. Rice,
in the Proceedings of the 2011 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August, 2011, Victoria, B.C., Canada, pages 274-279.
[pdf] (BEST PAPER)
"Ordering Techniques for ESOP-Based Toffoli Cascade Generation",
N. M. Nayeem and J. E. Rice,
in the Proceedings of the 2011 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August, 2011, Victoria, B.C., Canada, pages 274-279.
[pdf]
"On Designing a Ternary Reversible Circuit for Online Testability",
Md. R. Rahman and J. E. Rice,
in the Proceedings of the 2011 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August, 2011, Victoria, B.C., Canada, pages 119-124.
[preliminary pdf]
"Improving ESOP-based Synthesis of Reversible Logic",
N. M. Nayeem and J. E. Rice,
in Proceedings of the 2011 RM Workshop,
Tuusula, Finland, May 25-26, pp. 57-62.
[pdf]
"Online Testable Ternary Reversible Circuit",
M. R. Rahman and J. E. Rice,
in Proceedings of the 2011 RM Workshop,
Tuusula, Finland, May 25-26, pp. 71-79.
[pdf]
"New Considerations for Spectral Classification of Boolean Switching Functions", J. E. Rice, J. C. Muzio and N. Anderson,
VLSI Design, vol. 2011, Article ID 356137, 9 pages, 2011.
doi:10.1155/2011/356137
[online article]
2010
"Systolic Array Technique for Determining Common Approximate
Substrings", J. E. Rice and K. B. Kent,
Journal of Computer Science and Engineering,
May 2010, Volume 1, Number 1, pp. 1--9 [pdf]
"Using Autocorrelation Coefficients-based Cost Functions
in ESOP-based Toffoli Gate Cascade Generation", J. E. Rice and
V. Suen, in the proceedings of the 23rd IEEE Canadian Conference
on Electrical and Computer Engineering (CCECE),
Calgary, Canada, May 2010, pages 1--6
[pdf]
2009
"Properties of Autocorrelation Coefficients for Single-Output
Switching Functions", J.E. Rice, J.C. Muzio, N.A. Anderson and
R. Jansen,
International Journal of Computer Theory and Engineering (IJCTE), December 2009,
Volume 1, Number 5, pp. 546--555
[pdf]
"A Lightweight Architecture for Secure Two-Party Mobile Payment",
Y. Zhu
and J. E. Rice, in the Proceedings of the International Conference
on Computational Science
and Engineering (CSE)
August 29 - 31, Vancouver, B.C., Canada,
Volume 2 pages 326 - 333 [pdf]
"A Proposed Architecture for Secure Two-Party Mobile Payment", J. E. Rice and
Y. Zhu, in the Proceedings of the
2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing August 23-26, 2009, University of Victoria, Victoria, B.C., Canada,
pages 88 - 93
[pdf]
"The Autocorrelation Transform and its Application to the Classification of Boolean Functions", J. E. Rice, in the Proceedings of the
2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing August 23-26, 2009, University of Victoria, Victoria, B.C., Canada,
pages 94 - 99
[pdf]
"Toffoli Gate Cascade Generation Using ESOP Minimization and QMDD-Based
Swapping", J.E. Rice, K. Fazel,,
M. Thornton and K. B. Kent, in the Proceedings of
the Reed-Muller Workshop,
May 23-24 2009, Okinawa, Japan, pp. 63--72.
[pdf]
"Case Studies in Determining the Optimal FPGA Design for Computing Highly Parallelizable Problems", J.E. Rice and K.B.Kent,
IET Computers \& Digital Techniques, May 2009
Volume 3, Issue 3, p. 247-258.
[pdf]
2008
"An Introduction to Reversible Latches", J. E. Rice,
The Computer Journal 2008 51(6):700-709; doi:10.1093/comjnl/bxm116
[online access]. [bibtex pdf]
2007
"Investigating the Implementation of a 2DR-tree
on a FPGA", J. E. Rice, J. Schultz and W. Osborn,
in the Proceedings of the
5th Annual IEEE International Northeast Workshop on
Circuits and Systems (NEWCAS), August 5-8 2007, Montreal,
Quebec, Canada, pp. 646--649
[bibtex pdf].
"ESOP-based Toffoli Gate Cascade Generation", J. E. Rice,
M. Thornton and
K. Fazel, in the Proceedings of
the 2007 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
August 22-24, 2007,
Victoria, B.C., Canada, pp. 206-209
[pdf].
2006
"Implementation of a Spatial Data Structure on a FPGA",
J. E. Rice, W. Osborn and J. Schultz, in the
Proceedings of the Second International Joint Conferences on
Computer, Information, and Systems Sciences and Engineering
(CISSE),
December 4-14 2006, CDROM paper no. 549 (e-conference), published
by Springer, [pdf].
"An Analysis of Several Proposals for Reversible Latches", J. E. Rice,
in the Proceedings of the Second International
Joint Conferences on
Computer, Information, and Systems Sciences and Engineering
(CISSE), December 4-14 2006, CDROM paper no. 548 (e-conference), published
by Springer, [pdf].
"Balancing Motherhood and
a Career in the Sciences",
J. E. Rice, invited paper,
in the 2006 Graduate Students' Association Conference Proceedings
[GSA Proceedings].
(unrefereed)
"Gender and Programming: a sociolinguistic perspective"
(with K. Hansen), in the Proceedings of
the First Annual Gender Symposium, March 4 2006,
University of Lethbridge [symposium proceedings].
(unrefereed)
"A New Look at Reversible Memory Elements",
Authors: J. E. Rice, in the Proceedings of the International Symposium
on Circuits and Systems (ISCAS) 2006, CDRom paper 1628.pdf,
pp. 1243-1246
[pdf].
"A Systolic Array Techniques for Determining Common Approximate
Substrings",
Authors: J. E. Rice and K. B. Kent, in the Proceedings of
the International
Symposium on Circuits and Systems (ISCAS) 2006,
CDRom paper 1480.pdf
[pdf].
2005
"Reversible Logic Synthesis Example using a Transformation Based
Algorithm" (with B. Gergel), presented at the
ULSI Workshop 2005 [pdf].
(unrefereed)
"Determining a Method for Fast Autocorrelation Classification",
in the Proceedings of the IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing
(PACRIM) 2005, Aug. 24-26, Victoria, BC, Canada, CDROM paper number 338,
pages 661-664
[pdf].
"Making a Choice Between FDDs and BDDs",
in the Proceedings of
the International Workshop on Logic Synthesis (IWLS), Lake Arrowhead,
California, June 2005, pages 46-50
[pdf].
"Symmetrical, Dual and Linear Functions and Their Autocorrelation
Coefficients" (with R. Jansen), in the Proceedings of
the International Workshop on Logic Synthesis (IWLS), Lake Arrowhead,
California, June 2005, pages 30-35
[pdf].
"Hardware-Based Implementation of the Common Approximate
Substring Algorithm" (with K. B. Kent,
S. Van Schaick, and P. A. Evans),
in the Proceedings of the Euromicro Conference on
Digital System Design (DSD)
August 30 - September 3, 2005, Porto, Portugal, pages 314-320
[pdf].
"Instance-specific versus Parameter-specific Circuit Generation"
(with K. Kent, T. Ronda and Z. Yong),
in the Proceedings of the Engineering of Reconfigurable Systems and Applications (ERSA) Conference,
part of the International Multiconference on Computer Science and Computer
Engineering, June 27-30, 2005, Las Vegas, U.S.A, pages 243-246
[pdf].
"Antisymmetries in the Representation of Boolean and
Multi-Valued Functions" (with J. C. Muzio),
the Proceedings of the
the International Symposium on Multiple-ValuedLogic (ISMVL),
Calgary, Alberta, May 2005, pages 270-275
[pdf].
"Configurable
Hardware Solutions for Computing Autocorrelation Coefficients:
a Case Study" (with K. Kent, T. Ronda and Z. Yong),
in the Proceedings of the International Conference on
Field Programmable Gate Arrays (FPGA) 2005, Monterey California, Feb. 2005
[pdf].
2003
"Properties of Autocorrelation Coefficients" (with J. C. Muzio),
in the Proceedings of the IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing (PACRIM),
2003, Victoria, Canada, pp. 577-580
[pdf].
"Using Instance-Specific Circuits to Compute Autocorrelation
Coefficients" (with K. Kent),
in the Proceedings of the First Annual Northeast Workshop on
Circuits and Systems (NEWCAS), 2003, Montreal, Canada,
pages 61-64
[paper, word doc format].
"On the Use of Autocorrelation Coefficients in the Identification
of Three-Level Decompositions",
in the Proceedings of the International Workshop on Logic Synthesis
(IWLS) 2003, Laguna Beach, California, pp. 187-191
[ps format]
[pdf format].
"Autocorrelation Coefficients in the Representation and
Classification of Switching Functions", presented at
the first EDAA PhD Forum in conjunction with the
Design, Automation and Test in Europe Conference (DATE),
2003, Munich, Germany.
[abstract, ps format]
[poster, ppt format].
PhD Dissertation: "Autocorrelations Coefficients in the
Representation and Classification of Switching Functions",
University of Victoria, 2003
[zipped ps
format].
2002
"Use of the Autocorrelation Function in the Classification of
Switching Functions" (with J. C. Muzio),
in the Proceedings of the Euromicro Symposium
on Digital System Design: Architectures, Methods and Tools (DSD),
2002, Dortmund, Germany, pp 244-251
[ps format].
"Antisymmetries in the Realization of Boolean Functions" (with J. C. Muzio),
in the Proceedings of the International Symposium on Circuits and
Systems (ISCAS 2002),
May 26-29, Scottsdale, Arizona [ps format] [pdf format].
2000
"Methods for Calculating Autocorrelation Coefficients" (with J. C.
Muzio and M. Serra), in the proceedings of the
4th International Workshop on Boolean Problems Sept. 21-22 2000,
Freiberg, Germany, pp 69-76
[ps format] [presentation].
1999
"The Use of Autocorrelation Coefficients for Variable Ordering for ROBDDs"
(with J. C. Muzio and M. Serra) in the Proceedings of
the 4th International Workshop on
Applications of the Reed-Muller Expansion in Circuit Design 1999,
pages 185-196
[ps format].
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TR-CSJR1-2005: Projects Background in Reversible Logic
TR-CSJR2-2005:The
State of Reversible Sequential Logic Synthesis
TR-CSJR2-2007:Considerations for Determining
a Classification Scheme for Reversible Boolean Functions
TR-CSJR1-2012: ESOP-based methods for Toffoli gate cascade generation
TR-CSJR2-2012: Sociolinguistics in Programming: Background Material
Bibliography of Papers related to Reversible Logic
SYNTHESIS AND TESTING
OF REVERSIBLE TOFFOLI CIRCUITS MSc thesis,
N. M. Nayeem, University of Lethbridge, Lethbridge,
Alberta, 2011 (pdf).
ONLINE TESTING
IN TERNARY REVERSIBLE LOGIC, MSc thesis,
Md. Raqibur Rahman, University of Lethbridge, Lethbridge,
Alberta, 2011 (pdf).
A New Architecture For
Secure Two-Party Mobile Payment Transactions,
MSc thesis, Yunpu Zhu, University of Lethbridge, Lethbridge,
AB, 2010 (pdf).
The Classification
of Boolean Functions Using the Rademacher-Walsh Transform,
MSc thesis, N. Anderson, University of Victoria,
Victoria, BC, 2007 (pdf).
Autocorrelation Coefficients
in the Representation and Classification of Switching
Functions, PhD Dissertation, J.E. Rice,
University of Victoria, Victoria, BC, 2003 (pdf).
Variable Ordering for
ROBDD-Based FPGA Logic Synthesis,
MSc thesis, J. E. Rice (nee Crow), University of Victoria,
Victoria, BC, 1995 (ps format).
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